Approche ADL pour la modélisation d'architecture basée sur les contraintes (calcul de WCET)

La modélisation des systèmes temps-réel nécessite la connaissance de la borne supérieure des temps d'exécution possibles des tâches temps-réel, appelée temps d'exécution pire-cas ou WCET-Worst Case Execution Time. Le calcul du WCET par analyse statique est basée sur l'analyse du flot de contrôle du programme. Les chemins d'exécution du programme sont composés de séquences d'instructions, qu'on appelle les blocs de base, et des contrôles. Une étape de l'analyse statique, appelée analyse du pipeline, permet d'étudier l'impact de la micro-architecture sur le temps d'exécution des instructions du bloc de base. Le travail de cette thèse s'intéresse à l'analyse du pipeline pour le calcul du WCET. Cette étape du flotot de calcul du WCET prend en compte les caractéristiques du jeu d'instructions et les caractéristiques matérielles du processeur. On a alors besoin de spécifications haut-niveau de l'architecture logicielle et matérielle des processeurs. Nous considérons les langages de description d'architecture (Architecture Description Languages-ADL) pour la description du processeur. Les ADLs, comme Sim-nML, HARMLESS, LISA, sont utilisés pour la génération d'outils ciblés (simulateurs, assembleurs), la vérification, etc. Parmi les outils, OTAWA est un environnement pour l'analyse de temps, qui implémente différentes méthodes de calcul du temps d'exécution pire-cas. Actuellement, OTAWA utilise le langage Sim-nML pour la spécification du jeu d'instructions (le niveau ISA) de l'architecture. Ce travail de thèse est une contribution à OTAWA par une approche ADL pour l'analyse du pipeline. Le but étant d'améliorer l'expressivité en terme de description des processeurs, nous proposons une extension du langage de description Sim-nML, comme première contribution. Cette extension permet de supporter, en plus de la description du jeu d'instructions, la description matérielle de processeurs complexes. Elle permet aussi de séparer l'étape de description d'architecture de l'étape d'analyse et de calcul du temps. Cette extension permet une description déclarative des ressources disponibles et de leurs caractéristiques et aussi de superposer le modèle d'utilisation de ressources des instructions à la description initiale des instructions, qu'on appellera modèle d'exécution. La deuxième contribution de cette thèse consiste à mettre en place une nouvelle méthode pour le calcul du temps d'exécution d'un bloc de base. Nous proposons une méthode nouvelle pour le calcul du temps de bloc de base, basée sur la programmation par contraintes (Constraint Satisfaction Problem-CSP). Nous avons inscrit cette méthode dans une approche automatisée, basée sur la spécification ADL du processeur et sur une séquence d'instructions à analyser (le bloc de base). Nous utilisons des langages de spécification de contraintes et des outils de résolutions. Le principe est d'exprimer les propriétés structurelles et temporelles de l'architecture et des instructions avec des contraintes.The analysis of the worst-case execution time (WCET) is necessary in the design of critical real-time systems. To get sound and precise times, the WCET analysis of these systems must be performed on binary code and based on static analysis. Each execution path of the analyzed program is split into code snippets, called basic blocs. A pipeline analysis consists in modeling the execution of basic blocks on the pipeline and evaluating the impact of the hardware features on the corresponding execution costs. This thesis focuses on the pipeline analysis for WCET computation. The pipeline analysis considers the instruction set architecture and the hardware features of the processor. Then, a high level specification of the software and hardware architecture is needed. We consider Architecture Description Languages (ADL) for processors description. The ADLs, like Sim-nML, HARMLESS, LISA, are used for the generation of retargetable tools, such as simulators, assemblers, in verification, etc. OTAWA is a framework dedicated to the WCET computation that is able to integrate different kind of methods of computation. The instruction set architecture (the ISA level) is expressed in the Sim-nML language. Our work consists in extending the OTAWA framework with an ADL-based approach for pipeline analysis. The aim of our work has been to enhance the expressivity of OTAWA with regard to the processor description language. In order to do so, we first extend the Sim-nML language, to support both the instruction set description and the hardware description. The extended Sim-nML supports the description of hardware components features and superpose the resource usage model of the instructions, that we call execution model, to the initial description. This document also presents a new method to compute a basic bloc execution time. The proposed method is based on constraint programming (Constraint Satisfaction Problem-CSP). We integrated this method in an automated approach, based on the Sim-nML specification of the target processor and based on the instruction sequence to analyse (the basic bloc). We use constraints to express the structural and the temporal properties of the architecture and the instructions, which resolution provides the time cost of basic blocs of a program. Our method uses well known constraint specification languages and resolution tools. The experimentations provide more accurate times. During this thesis, we have been concerned with the formalization of the architecture specification and the results validation. We propose a logic based description of the static and dynamic properties of the architecture and of the basic bloc instructions, presented as a set of high-level constraints. The goal is to provide a reusable library in which the architectuser can find a set of reusable quantitative properties, that assist him in the formalization of the architecture specification. A validation and animation tool was developed based on timed automata. We validate time results provided by the constraints solvers. We generate animated views that assist the architect to validate general dynamic properties and replay the instructions execution

A constraint-based WCET computation framework

National audienceOTAWA is a tool dedicated to the WCET computation of critical real-time systems. The tool was enhanced in order to take into account modern micro-architecture features, through an ADL-based approach. Architecture constraints are expresses such that they can be solved by well known efficient constraint solvers. In this paper, we present how we could describe some complex architecture features using the Sim-nML language. We are also concerned by the validation and the animation point of views

Formal Architecture Specification for Time Analysis

International audienceWCET calculus is nowadays a must for safety critical systems. As a matter of fact, basic real-time properties rely on accurate timings. Although over the last years, substantial progress has been made in order to get a more precise WCET, we believe that the design of the underlying frameworks deserve more attention. In this paper, we are concerned mainly with two aspects which deal with the modularity of these frameworks. First, we enhance the existing language Sim-nML for describing processors at the instruction level in order to capture modern architecture aspects. Second, we propose a light DSL in order to describe, in a formal prose, architectural aspects related to both the structural aspects as well as to the behavioral aspects

Hardware architecture specification and constraint-based WCET computation

International audienceThe analysis of the worst-case execution times is necessary in the design of critical real-time systems. To get sound and precise times, the WCET analysis for these systems must be performed on binary code and based on static analysis. OTAWA, a tool providing WCET computation, uses the Sim-nML language to describe the instruction set and XML files to describe the microarchitecture. The latter information is usually inadequate to describe real architectures and, therefore, requires specific modifications, currently performed by hand, to allow correct time calculation. In this paper, we propose to extend Sim-nML in order to support the description of modern microarchitecture features along the instruction set description and to seamlessly derive the time calculation. This time computation is specified as a constraint solving problem that is automatically synthesized from the extended Sim-nML. Thanks to its declarative aspect, this approach makes easier and modular the description of complex features of microprocessors while maintaining a sound process to compute times